Name: Gu Haiyun

Position: Lecturer

Degree: Ph.D.

Research interests: Network-on-Chip, Reconfigurable Computing

Programs:

2012-2015 Principle Investigator

Project name: Research on the Traffic Model and Simulation of Dynamically Reconfigurable Network-on-Chip

Sponsored by: Science & Technology Program of Shanghai Maritime University

2010-2011 Visiting Scholar

Project name: Simulator of Network-on-Chip

Sponsored by: Embedded System Lab, Colorado State University, USA

2008-2010 Principle Investigator

Project name: Mapping Algorithm of Dynamically Reconfigurable Network-on-Chip

Sponsored by: Science & Technology Program of Shanghai Maritime University

2006-2009 Principle Investigator

Project name: Design Methodology of Network-on-Chip

Sponsored by: Science Foundation for the Excellent Youth Scholars of Shanghai Municipal Education Commission

SELECTED PUBLICATIONS：

1. Gu Haiyun, “A Review of Research on Network-on-Chip Simulator”, 2011 International Conference on Electric and Electronics. （EI 20120714770175）

2. Gu Haiyun, Renlei, Chen Shurong, SunShu, Dynamic Reconfigurable SoC: architecture, computing model and design flow, Journal of information & computational science, volume 5, Number 6, 2009 (EI20092712163321)

3. Gu Haiyun, Chen Shurong, Partial reconfiguration bitstream compression for Virtex FPGAs, International Congress on Image and Signal Processing, May 27-30 2008, Sanya, China (EI20083911583981)

4. Gu Haiyun, Li Changwen, Sunshu, Research on Mapping Algorithm of irregular mesh NoC for Portable Multimedia Appliances. The IET Communications Conference on Wireless, Mobile and Sensor Networks Dec 12-14 2007, Shanghai, China (EI20091311975640)

5.Gu Haiyun, Li Li, Xu Juyan, Gao Minglun, Lossless Configuration Bitstream Compression for Virtex FPGAs, Computer Research and Development, May 2006 (EI062910013969)